1. Field of the Invention
The present invention relates to a process for producing a semiconductor memory device and a semiconductor memory device, and more specifically, it relates to a process for producing a semiconductor memory device and a semiconductor memory device that have a floating gate and a control gate with an asymmetric source/drain region.
2. Description of the Related Art
A process for producing a semiconductor memory device having an asymmetric source/drain region is proposed, for example, in Japanese Patent Application Laid-open HEI 4(1992)-137558.
The process for producing a semiconductor memory device according thereto will be described below. FIG. 16(a) to FIG. 17(g) are cross sectional views on line X-Xxe2x80x2 in FIG. 15(a), and FIG. 16(a) to FIG. 17(gxe2x80x2) are cross sectional views on line Y-Yxe2x80x2 in FIG. 15(a).
As shown in FIGS. 16(a) and 16(axe2x80x2), on an active region of a P type semiconductor substrate 21, a tunnel oxide film having a film thickness of about 10 nm, a phosphorous-doped polycrystalline silicon film 3 of about 100 nm and a silicon nitride film 4 of about 100 nm are sequentially deposited, and the silicon nitride film 4, the polycrystalline silicon film 3 and the tunnel oxide film 2 are sequentially etched by a reactive ion etching using a resist R21 (see FIG. 15(b)) patterned by a photolithography technique as a mask, so as to pattern for a floating gate.
After removing the resist R21, as shown in FIGS. 16(b) and 16(bxe2x80x2), arsenic ions, for example, are implanted at 0xc2x0 with respect to the normal line of the substrate (hereinafter referred to as xe2x80x9c0xc2x0xe2x80x9d) with an implantation energy from about 5 to about 40 keV and a dose from about 5xc3x971012 to about 5xc3x971013 ions/cm2 using the floating gate as a mask, so as to form a low concentration impurity layer 25.
Thereafter, as shown in FIGS. 16(c) and 16(cxe2x80x2), after covering the low concentration impurity layer 25 with a resist R24 by a photolithography technique, arsenic ions are implanted at 0xc2x0, with an implantation energy from about 5 to about 40 keV and a dose from 1xc3x971015 to 1xc3x971016 ions/cm2, so as to form a high concentration impurity layer 26.
After removing the resist R24, as shown in FIGS. 16(d) and 16(dxe2x80x2), a silicon oxide film to be an insulating film is deposited by a CVD (chemical vapor deposition) method to about 150 nm, and is etched back by a reactive ion etching, so as to form a side wall spacer 28 on a side wall of the floating gate. At this time, the width of the side wall spacer 28 is determined in such a manner that the high concentration impurity layer 26 is not present immediately under the side wall spacer 28 on the side of the low concentration impurity layer 25.
Subsequently, as shown in FIGS. 16(e) and 16(exe2x80x2), arsenic ions, for example, are implanted at 0xc2x0, with an implantation energy from about 5 to about 40 keV and a dose from 1xc3x971015 to 1xc3x971016 ions/cm2 using the side wall spacer 28 as a mask, so as to form a high concentration impurity layer 29.
Thereafter, the impurities are activated by a thermal treatment. A silicon oxide film to be a dielectric film is deposited by a CVD method to a thickness from about 400 nm to about 600 nm and is subjected to a CMP (chemical mechanical polishing) method, so as to fill a silicon oxide film 30 in a space between the floating gates. The silicon nitride film 24 is then removed by hot phosphoric acid. Subsequently, as shown in FIGS. 17(f) and 17(fxe2x80x2), a phosphorous-doped polycrystalline silicon film 31 is deposited in a thickness of about 100 nm to increase the gate coupling ratio.
Thereafter, as shown in FIGS. 17(g) and 17(gxe2x80x2), the polycrystalline silicon film 31 is processed by a reactive ion etching using a resist R22 patterned by a photolithography technique (see FIG. 15(b)), so as to form a stacked floating gate on the polycrystalline silicon film 23. After removing the resist R22, a silicon oxide film of 6 nm is deposited by a thermal oxidation on the surface of the stacked floating gate, and a silicon nitride film of 8 nm and a silicon oxide film of 6 nm are deposited thereon by a CVD method, in this order, so as to form an ONO film 32 (silicon oxide film/silicon nitride film/silicon oxide film) to be a dielectric film between a floating gate and a control gate. A polycide film (comprising a polycrystalline silicon film doped with phosphorous ions as an impurity of 100 nm and a tungsten silicide film of 100 nm) to be a control gate material is then deposited to a thickness of about 200 nm, and the polycide film, the ONO film 32, the polycrystalline silicon film 31 and the polycrystalline silicon film 23 are sequentially etched by a reactive ion etching using a resist R23 patterned by a photolithography technique (see FIG. 15(b)) as a mask, so as to form a control gate 33 and a floating gate 34. After removing the resist R23, boron ions, for example, are implanted at 0xc2x0 with an implantation energy from about 10 to about 40 keV and a dose from 5xc3x971012 to 5xc3x971013 ions/cm2 using the control gate 33 as a mask, so as to form an impurity layer 35 for isolation of memory elements.
Thereafter, according to the known process, an interlayer dielectric film is formed, and a contact hole and metallic wiring are formed.
An equivalent circuit of the source/drain asymmetric semiconductor memory device thus formed is shown in FIG. 18.
In FIG. 18, Tr.00 to Tr.32 are memory cells having a floating gate, WL0 to WL3 are word lines connected to the control gates of the memory cells, and BL0 to BL3 are bit lines connected to the drain/source common diffusion wiring layers of the memory cells. The word line WL0 is connected to the control gates of Tr.00, Tr.01 and Tr.02, and the word line WL1 is connected to the control gates of Tr.10, Tr.11 and Tr.12, respectively (the rest is omitted). The bit line BL1 is connected to the drains of Tr.01, Tr.11, Tr.21 and Tr.31 or the sources of Tr.00, Tr.10, Tr.20 and Tr.30, and the bit line BL2 is connected to the drains of Tr.02, Tr.12, Tr.22 and Tr.32 or the sources of Tr.01, Tr.11, Tr.21 and Tr.31.
The operation voltages of reading, writing and erasing a selected Tr.11 in FIG. 18 are shown in Table 1. Furthermore, FIG. 19 shows the state of reading Tr.11, FIG. 20 shows the state of writing Tr.11, and FIG. 21 shows the state of erasing Tr.10 to Tr.12 including Tr.11 connected to the word line WL1.
It is assumed that the writing of the memory cell is defined, for example, as Vth less than 2 V, and the erasing thereof is defined, for example, as Vth greater than 4 V.
The writing method will be described with reference to FIG. 19 and Table 1. When a voltage of 3 V is applied to the control gate, the substrate and the drain are grounded and a voltage of 1 V is applied to the source, the information in the memory cell can be read out by detecting whether or not an electric current i flows between the source and the drain.
The reading method will be described with reference to FIG. 20 and Table 1. Upon writing in Tr.11, as shown in Table 1, a voltage of xe2x88x9212 V is applied to the control gate, the substrate is grounded, and a voltage of 4 V is applied to the drain, whereby electrons are drawn from the floating gate by using an FN tunnel electric current flowing in a thin oxide film in the overlapping region of the drain and the floating gate. At this time, while a voltage 4 V is also applied to the source of Tr.10 that is common to the drain applied with the positive voltage, a depletion layer spreads on the side of the substrate owing to the thin impurity concentration, and an electric current actually applied to the thin oxide film in the overlapping region of the drain and the floating gate becomes insufficient to generate the FN tunnel electric current. As a result, the writing selectively occurs only in such a memory cell that has a floating gate overlapping the drain side (high concentration impurity layer side).
The erasing method will be explained with reference to FIG. 21 and Table 1. Upon erasing Tr.11, when a voltage of 12 V is applied to the control gate and a voltage of xe2x88x928 V is applied to the source/drain and the substrate, electrons can be injected in the floating gate by using an FN tunnel electric current flowing in the entire channel. At this time, the states of the applied voltage between the control gate and the source/drain/substrate of Tr.10 to Tr.12 connected to Tr.11 through the word line WL 1 are the same as each other, and the memory cells connected to the selected word line are simultaneously erased.
In the case where the width between the floating gates 34 is reduced for miniaturization in the semiconductor memory cell described in the foregoing, when the width of the low concentration impurity layer 25 is simply decreased, the impurity concentration of the overlapping region of the source region and the floating gate 34, which is essentially low, is increased due to the impurity diffusion from the high concentration impurity layer 29, whereby erroneous writing may occur in the adjacent non-selected cell. Therefore, in order to ensure the asymmetry of the low concentration impurity layer 25 and the high concentration impurity layer 26 to prevent the erroneous writing in the adjacent non-selected cell, the width of the side wall spacer is necessarily about 150 nm.
The bit line requires a sufficient impurity concentration and a sufficient cross sectional area in order to suppress the wiring resistance. Furthermore, the overlapping region of the drain region and the floating gate 34 necessarily has a sufficient impurity concentration for writing, and thus requires such a impurity concentration and a cross sectional area that the impurity concentration is not remarkably decreased. Therefore, the width of the high concentration impurity layer is necessarily about 300 nm.
Moreover, the high concentration impurity layer 26 should be certainly arranged immediately under the side wall spacer on the side of the high concentration impurity layer 26 with defining the position of the photoresist R24 in such a manner that the high concentration impurity layer 26 does not spread to the position immediately under the side wall spacer on the side of the low concentration impurity layer 25. Therefore, the overlapping accuracy of the floating gate and the photoresist R24 should be strictly considered. That is, in the case where the overlapping accuracy is about 150 nm, the width of the floating gate 34 is necessarily about 600 nm at the lowest.
Owing to the foregoing reasons, the width of the floating gate 34, i.e., the width of the bit line, is difficult to be decreased, and various problems arise in the further miniaturization of a semiconductor memory device.
The invention has been developed in view of the foregoing problems associated with the conventional art, and an object thereof is to provide a process for producing a semiconductor memory device and a semiconductor memory device that have a floating gate and a control gate, and can prevent an increase in resistance of a bit line arranged between the floating gates in such a semiconductor memory device that the source/drain region is asymmetric, while the bit line width can be decreased.
The preset invention provides with a process for producing a semiconductor memory device comprising the steps of:
(a) forming a floating gate on a semiconductor substrate through a dielectric film;
(b) forming a side wall spacer comprising an insulating film on a side wall of the floating gate;
(c) forming a groove by etching the semiconductor substrate using the side wall spacer as a mask; and
(d) forming a low concentration impurity layer from one side wall to a bottom surface of the groove by an oblique ion implantation to the resulting semiconductor substrate, and forming a high concentration impurity layer from the other side wall to the bottom surface of the groove by an inverse oblique ion implantation.
Further, the present invention provides with a process for producing a semiconductor memory cell comprising the steps of:
(a) forming a floating gate on a semiconductor substrate through a dielectric film;
(x) forming a low concentration impurity layer on a surface of the semiconductor substrate by an ion implantation using the floating gate as a mask, and forming a high concentration impurity layer only on the other side than the floating gate by an oblique ion implantation to the surface of the semiconductor substrate;
(bxe2x80x2) forming a side wall spacer comprising an insulating film on a side wall of the floating gate in a manner in that only the low concentration impurity layer is arranged immediately under the floating gate on one side of the floating gate;
(cxe2x80x2) forming a groove by etching the semiconductor substrate using the side wall spacer as a mask to a depth deeper than a junction of the low concentration impurity layer and the high concentration impurity layer; and
(dxe2x80x2) electrically connecting the low concentration impurity layer and the high concentration impurity layer by conducting an ion implantation inside the groove.
Moreover, the present invention provides with a process for producing a semiconductor memory device comprising the steps of:
(a) forming a floating gate on a semiconductor substrate through a dielectric film;
(w) covering a side wall of the floating gate with an oxide film;
(x) forming a low concentration impurity layer on a surface of the semiconductor substrate by an ion implantation using the floating gate as a mask, and forming a high concentration impurity layer only on the other side than the floating gate by an oblique ion implantation to the surface of the semiconductor substrate;
(y) extending the low concentration impurity layer and the high concentration impurity layer to a position under the floating gate by a thermal treatment;
(cxe2x80x2) forming a groove by etching the semiconductor substrate using the oxide film as a mask to a depth deeper than a junction of the low concentration impurity layer and the high concentration impurity layer; and
(dxe2x80x2) electrically connecting the low concentration impurity layer and the high concentration impurity layer by conducting an ion implantation inside the groove.
Furthermore, the present invention provides with a semiconductor memory device comprising a plurality of memory cells comprising
a substrate which has at least two grooves formed therein and source/drain regions formed on sidewalls of the grooves,
a floating gate formed on the semiconductor substrate between the grooves through a tunnel oxide film,
a control gate formed on the floating gate through an interlayer capavitive film,
wherein the source/drain regions comprise a low concentration impurity layer and a high concentration impurity layer, the low concentration impurity layer being formed on one sidewall of each the grooves and the high concentration impurity layer being formed on another sidewall of each the grooves,
in each of the grooves, the low concentration impurity layer and the high concentration impurity layer are connected to each other through an impurity layer formed on a bottom surface of the groove.